Arbetsbeskrivning

Veritaz is a leading IT staffing solutions provider in Sweden, committed to advancing individual careers and aiding employers in securing the perfect talent fit. With a proven track record of successful partnerships with top companies, we have rapidly grown our presence in the USA, Europe, and Sweden as a dependable and trusted resource within the IT industry.

Assignment Description:

We are looking for a Senior ASIC Designer to join our dynamic team.

What you will work on:

• Contribute to the development and design of complex ASICs and large FPGA systems.
• Work with multi-clock domain environments to ensure seamless integration.
• Collaborate on projects involving both new designs and the optimization of existing ASIC solutions.
• Utilize System Verilog to drive development processes.
• Communicate and collaborate effectively with team members to deliver high-quality results.

What you bring:

• 5+ years of experience in ASIC development.
• Proven experience working with complex ASIC and/or large FPGA designs.
• Expertise in multi-clock domain designs and handling the associated challenges.
• Strong proficiency in System Verilog.
• Excellent English communication skills, both written and verbal.

Meritorious if you have:

• Experience in systemization and architecture design.
• Knowledge of backend processes including timing constraints, timing optimization, and formal verification.
• Familiarity with UVM verification methodologies.
• Scripting skills for design automation.
• Background in the telecom sector.