Senior ASIC Verifier – 10352
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Besök hemsida veritaz.se
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Publicerad 2024-09-12

Veritaz is a leading IT staffing solutions provider in Sweden, committed to advancing individual careers and aiding employers in securing the perfect talent fit. With a proven track record of successful partnerships with top companies, we have rapidly grown our presence in the USA, Europe, and Sweden as a dependable and trusted resource within the IT industry.

Assignment Description:

We are looking for a Senior ASIC Verifier to join our dynamic team.

What you will work on:

  • Participate in the verification of complex ASIC designs, collaborating with teams on both new and existing projects.
  • Apply advanced verification methodologies, including UVM and SystemVerilog, to ensure the functionality and performance of ASIC and large FPGA designs.
  • Perform IP block verification and handle multi-clock domain environments.
  • Collaborate closely with design and verification engineers to define test plans, structure test benches, and execute verification strategies.
  • Contribute to improving verification processes and methodologies for better efficiency and coverage.
  • Engage in continuous learning and adaptation to emerging trends and technologies in ASIC verification.

What you bring:

  • At least 4 years of experience in ASIC verification, with a deep understanding of complex ASIC or large FPGA designs.
  • Strong expertise in UVM (Universal Verification Methodology) and SystemVerilog, with 1-2 years of hands-on UVM experience.
  • Experience in IP block verification and handling multi-clock domains.
  • Excellent communication skills in English, both spoken and written.
  • Proven ability to work effectively within teams, contributing to collaborative and productive environments.

Preferred qualifications:

  • Experience in structuring and designing test benches.
  • Leadership skills with the potential to guide junior team members or lead verification efforts.
  • Knowledge of RTL (Register Transfer Level) design.
  • Scripting abilities for automation and process improvements.
  • Lab experience for hands-on debugging and validation.
  • Background in telecommunication projects or environments.



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