Veritaz is a leading IT staffing solutions provider in Sweden, committed to advancing individual careers and aiding employers in securing the perfect talent fit. With a proven track record of successful partnerships with top companies, we have rapidly grown our presence in the USA, Europe, and Sweden as a dependable and trusted resource within the IT industry.

Assignment Description:

We are looking for a Senior ASIC Verification Engineer to join our dynamic team

What you will work on:

• Collaborate with a team of 7-10 ASIC verifiers to support our telecom sector customer.
• Engage in a blend of IP design/verification and various levels of SubSys integration/verification.
• Utilize remote work flexibility within the European time zone.

What you bring:

• 3 or more years of experience in ASIC verification.
• Proficiency in UVM, with at least one year of hands-on experience preferred.
• Background in complex ASIC and/or large FPGA design.
• Expertise in IP block verification and managing multi clock domains.
• Familiarity with RTL languages including Verilog, VHDL, and/or SystemVerilog.
• Strong English communication skills, both verbal and written.
• Experience in test bench structuring and design.
• Demonstrated leadership qualities and the ability to support junior team members.
• Knowledge of RTL design principles and scripting skills.
• Understanding of telecommunication concepts and technologies.