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Publicerad 2024-03-26

Xenergic AB is a high-tech semiconductor company providing high-speed, low-power memory solutions in advanced technology nodes. These memories are targeted for market segment ranging from IoT and mobile applications to high-end servers. We are looking for a highly motivated Senior Digital Back-End Designer with a proven track record in digital circuit design to join our team to contribute to validating the next generation of embedded memory solutions. As a Senior Digital Designer at Xenergic, you will handle integrating memory blocks into designs, carefully debugging and validating front-end and back-end memory views, and leading the development and approval of test designs for fabrication in various technology nodes.

The key responsibilities in this position:

As a Digital ASIC Designer specializing in Physical Design (PnR) and Back-End Design, you will be responsible for:

  • Leading and participating in the physical design and implementation of digital ASICs.
  • Utilizing industry-standard EDA tools for synthesis, floor planning, place and route (PnR).
  • Implementing power grid, clock tree synthesis, and signal integrity optimization.
  • Conducting static timing analysis (STA) to meet timing closure requirements.
  • Collaborating with RTL designers and SRAM developers to ensure design goals are met.
  • Troubleshooting and resolving physical design-related issues.
  • Detecting and helping to debug the issues seen in the integration flow related to the memory views

Required Skills:

To be successful in this role, candidates should possess the following qualifications and skills:

  • Bachelor's degree or higher in Electrical Engineering, Computer Engineering, or a related field.
  • Fluency in English (Swedish not required)
  • Proven experience in ASIC physical design and back-end design (5yrs+), including deep submicron technologies (nm).
  • Proficiency in EDA tools such as Cadence (preferred), Synopsys, or Mentor Graphics for PnR.
  • Strong knowledge of clock tree synthesis, power grid design, and signal integrity analysis.
  • Familiarity with scripting languages like TCL, or Python for automation.
  • Solid understanding of ASIC design principles and methodologies.
  • Experience with static timing analysis (STA) and timing closure techniques.
  • Excellent problem-solving skills and attention to detail.
  • Effective communication and teamwork abilities.

Preferred Qualifications (Not Mandatory):

While not required, the following qualifications and experiences would be considered a plus:

  • Experience with advanced technology nodes (22nm, 16nm, 5nm, or below).
  • Expertise with Cadence design flow for PnR, timing closure and signing off the test designs.
  • Knowledge of DFT (Design for Test) principles.
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